I'm doing a little work on the Decapede project. I don't understand some features of their MOSFET gate driver although it looks like it should be a standard totem pole driver, so I am seeking advice. Here is the current driver and my proposed new driver (in reverse order!)
[attachment 25376 gat_drivers.png]
I don't know if I am missing something obvious, but the things that puzzle me are:
1. The 15V zener diode D7 seems to be superfluous, I can't see it ever does anything. The gate voltage should never go above 12V.
2. The pull down R67 also seems ineffective, since 12V is derived from 24V. OTOH, FET3 might not be driven by the CPU or have pull ups enabled, so I moved the pull down to the input, which is what we do now on RAMPS_FD.
3. The 3 resistors R61, R65 and R66 are 1210 packages. I can't see why they need to be, 0805 should work fine here?
4. I can't see a need for R65 and R66, or why there is 15R on the low side and 30R on the high side.
5. I added a flyback diode D16 across the output, they definitely help reduce voltage peaks
So I think my new method should perform better and have a smaller footprint. Any comments?
[attachment 25376 gat_drivers.png]
I don't know if I am missing something obvious, but the things that puzzle me are:
1. The 15V zener diode D7 seems to be superfluous, I can't see it ever does anything. The gate voltage should never go above 12V.
2. The pull down R67 also seems ineffective, since 12V is derived from 24V. OTOH, FET3 might not be driven by the CPU or have pull ups enabled, so I moved the pull down to the input, which is what we do now on RAMPS_FD.
3. The 3 resistors R61, R65 and R66 are 1210 packages. I can't see why they need to be, 0805 should work fine here?
4. I can't see a need for R65 and R66, or why there is 15R on the low side and 30R on the high side.
5. I added a flyback diode D16 across the output, they definitely help reduce voltage peaks
So I think my new method should perform better and have a smaller footprint. Any comments?