IMO the zener is there to limit the gate voltage to 15V.
The only way I could see that happening is getting drain to gate leakage on the FET that is being driven. No idea how likely that is in this setup.
Might be worth looking at one of those integrated driver chips that were discussed in the RAMPS-FD thread. Probably cheaper, definitely less component count, and simpler to integrate.
The only way I could see that happening is getting drain to gate leakage on the FET that is being driven. No idea how likely that is in this setup.
Might be worth looking at one of those integrated driver chips that were discussed in the RAMPS-FD thread. Probably cheaper, definitely less component count, and simpler to integrate.