Yes the IRL3808 looks better to me too, mainly because it has half the on-resistance of the other, so when it conducts it dissipates less. First check thingy i would look for Ids versus Vgs graph. So our Vgs is 5v, need to make sure 5v gate opens the mosfet enough for more than 12.5++A of current to pass. If it would open less than that, it would operate in partially opened manner and it would burn instantly. This is in a graph which shows Ids in relation to Vgs, possibly in relation to others but those are less important. So our Vgs=5v produces more than our target current (preferably much more), then the mosfet will be fully open for that current and will operate like it should. Second datasheet check, with the Ron and overall math of losses like I^2*Ron like in that reprap wiki page, we make sure that when mosfet conducts fully, it dissipates low power, and that is low enough to be manageable in temperature terms. But as in the posts before we talked about switching losses, its worth to say that these dont appear anywhere yet, but if we will get anything like that, then will just add up to the conduction losses. So the conduction losses should have a hefty headroom for other types of losses.
When power mosfet can only be fully opened or closed, it works like a switch. The R(on) is a characteristic behaviour of a this situation where a mosfet conducts fully. Which is the only way these power mosfets are supposed to work. So almost all datasheet is centric to this situation. The Ron makes sense, this is why it has to be chosen a low value, small Ron means low conduction losses, but its not the only type of losses, there are switching losses. You can google "switching losses calculation". When the mosfet is partially opened, it works like an amplifier or a ttl gate with a pullup resistor, this is the domain of small signal mosfets. It produces a voltage output that depends on the gate voltage. In this situation the mosfet does not have a R(on) because it can not be modeled as a resistor. It has and entirely different model which implies relatively bigger losses than i2r. A small signal mosfet can operate in this mode because its in mA range and "bigger" losses only translate to less than 1A or so, in range of usual rating of a to-92 and its manageable for small ones, but not manageable for big power fet. So every time when mosfet gate goes from 0v to 5v, the mosfet changes from not conducting to fully conducting, and this transition means it goes fast through operation mode above where loses are big as mosfet is partially open and where R(on) model does not apply. Since we give the command to digitalwrite from zero going to 5v, the uC pin output has a rise time that should be in atmel datasheet. Also this pin has a low current output and tied to a fet gate with significant parasitic capacitance which needs to fully charge to get it to 5v. Even then, the mosfet itself has a rise time delay. So everything is "delayed", add up rise times, add up the delay of the gate charging, and there will be a small transition period when the mosfet is only partially opened and losses are huge. Small period but huge losses. If we have this transition often enough, it adds up and it forms switching losses. But one thing to note, our power mosfets datasheet do not provide much along the lines of this mode of operation because simply its not supposed to work like this.
So, nor switching losses neither that inductive spike made by parasitic inductance, neither of these are shown in that Ron graph because that graph is only for fully conducting mosfet, and that Ron is only relevant in terms of full conduction, and irrelevant in any other cases. The state when mosfet is partly opened does not actually have Ron at all, its entirely different math, a nightmare in terms of power dissipation. But all in all, switching losses depend first thing on how often we switch, hence the simplest way to mitigate them is to lower the switching frequency, or to avoid switching if possible. Also depends on how fast we switch, but if we want to change that it will take expensive gate drivers, because those will have more energy, in comparable terms those will have 3-4-5 amps peaks capacity instead of the uC pin with has something in miliamps range.
When power mosfet can only be fully opened or closed, it works like a switch. The R(on) is a characteristic behaviour of a this situation where a mosfet conducts fully. Which is the only way these power mosfets are supposed to work. So almost all datasheet is centric to this situation. The Ron makes sense, this is why it has to be chosen a low value, small Ron means low conduction losses, but its not the only type of losses, there are switching losses. You can google "switching losses calculation". When the mosfet is partially opened, it works like an amplifier or a ttl gate with a pullup resistor, this is the domain of small signal mosfets. It produces a voltage output that depends on the gate voltage. In this situation the mosfet does not have a R(on) because it can not be modeled as a resistor. It has and entirely different model which implies relatively bigger losses than i2r. A small signal mosfet can operate in this mode because its in mA range and "bigger" losses only translate to less than 1A or so, in range of usual rating of a to-92 and its manageable for small ones, but not manageable for big power fet. So every time when mosfet gate goes from 0v to 5v, the mosfet changes from not conducting to fully conducting, and this transition means it goes fast through operation mode above where loses are big as mosfet is partially open and where R(on) model does not apply. Since we give the command to digitalwrite from zero going to 5v, the uC pin output has a rise time that should be in atmel datasheet. Also this pin has a low current output and tied to a fet gate with significant parasitic capacitance which needs to fully charge to get it to 5v. Even then, the mosfet itself has a rise time delay. So everything is "delayed", add up rise times, add up the delay of the gate charging, and there will be a small transition period when the mosfet is only partially opened and losses are huge. Small period but huge losses. If we have this transition often enough, it adds up and it forms switching losses. But one thing to note, our power mosfets datasheet do not provide much along the lines of this mode of operation because simply its not supposed to work like this.
So, nor switching losses neither that inductive spike made by parasitic inductance, neither of these are shown in that Ron graph because that graph is only for fully conducting mosfet, and that Ron is only relevant in terms of full conduction, and irrelevant in any other cases. The state when mosfet is partly opened does not actually have Ron at all, its entirely different math, a nightmare in terms of power dissipation. But all in all, switching losses depend first thing on how often we switch, hence the simplest way to mitigate them is to lower the switching frequency, or to avoid switching if possible. Also depends on how fast we switch, but if we want to change that it will take expensive gate drivers, because those will have more energy, in comparable terms those will have 3-4-5 amps peaks capacity instead of the uC pin with has something in miliamps range.