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bobc
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Cefiar
Actually the pull-up in most cases goes to the +VGATE line, which will definitely drive the FETs.
I think we may need to bite the bullet and either switch to P-channel FET's in place of the DMN2075U's, or go for a proper gate driver.
uncle_bob gives me a thought. If we used HCT logic for the buffers and drive them from 5V, they will output 5V and accept either 3.3V or 5V as input. The advantage is that we may be able to drive the big FETs directly, and more importantly drive them with positive logic. That means we can pull the gates to 0V, so if 3V or 5V are not present the FETs will be off.
That makes a lot of sense, and removes a whole lot of components (4 DMN2075U's and all their associated resistors). It does mean we're not pushing the FETs as hard as they could be, but it'll be a lot better than just using 3.3V.
We could then lose the 12V regulator and put in a reasonable 5V supply to take the load off the Due completely. We could even power the Due's 5V directly off it, which bypasses any issues with the Due's on-board regulator.
Another advantage: By moving all the pull-ups to pull-downs, it will definitely reduce all the VCC tracks running everywhere for them.
